To generate the high-speed clock required at the Master side, a PLL-based Clock Multiplier is typically used. In the D-PHY architecture:

• A Clock Multiplier Unit (CMU) is assumed to exist outside the PHY block.

• The CMU generates the high-frequency clock that drives the PHY's High-Speed Clock Lane.

• However, implementation details are flexible — the CMU may be integrated inside the PHY depending on design choices.

This separation is architectural only, allowing system designers freedom in how they package the clock generation circuitry.